1. Field of the Invention
The present invention relates to a synchronization device for output stages, particularly for electronic memories.
2. Discussion of the Related Art
It is known that there are two fundamental control pins in electronic memories. The first one, CEN (inverted chip enable), is the pin that enables the memory. The second one, OEN (inverted output enable), is the pin that enables the output stage of the memory.
FIG. 1 is a block diagram of a possible conventional memory, wherein the memory circuit is designated by the reference numeral 1. The memory circuit sends the data to a latch circuit 2, which stores the data before sending them to the output stage 3. The memory circuit 1 is enabled by the CEN signal, that is to say, the circuit is enabled when said signal is equal to "0". The CEN signal and the OEN signal constitute the inputs of a NOR gate 4 which enables the output stage 3 if both input signals are "0".
Accordingly, if the OEN signal is at logic level "1", the output stage 3 is set to a high impedance, and this allows the logic to communicate with the interior of the memory. If instead the OEN signal is set to logic level "0", the output stage 3 is enabled to send out the data produced within the memory. This second operating mode is characterized by a response time that is faster than the corresponding time for the propagation of the data in the memory circuit 1 required to fully read the CEN signal. This means that the output stage 3 can switch randomly or on the basis of data which had been read earlier and is therefore obsolete.
It is known that switching on the outputs produces severe noise on the internal circuits of the memories and in general slows down the read times; the more this event occurs asynchronously and the higher the number of outputs, the slower the read time. Accordingly, it is desirable to avoid false switchings in order to achieve best performance. To deal with this variability in read times, a LOAD signal is generated within the memory circuit, and activates the latch circuit 2 when the dam from the memory circuit 1 reaches it. However, this has no effect on the output stage 3, which may still include false or useless data.